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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Cache Management Instructions

The instructions described in Table 40-11 on page 1057 can be used to manage the processor caches.

Table 40-11. Cache Management Instructions
InstructionDescription
CLFLUSHCache Line Flush (introduced in the Pentium® 4):
  • When executed, the processor uses the linear address of the specified one-byte memory operand and performs a lookup in all of the processor's caches (including the Trace Cache). This instruction has no effect if the line is not in any of the caches. The line is invalidated in any cache that contains it. However, if the line is in the modified state, it is also written back to system memory.

  • The memory type (as specified by the MTRRs and the PTE or PDE) does not affect this instruction in any way. ...

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