HT and the FSB
When a code or data request misses the processor caches and must be forwarded upstream to system memory, the request must be queued in the processor's FSB interface. The FSB interface treats requests issued by the two logical processors on a first-come, first-serve basis.
When a transaction is forwarded onto the FSB, the Agent ID issued in the transaction's Request Phase is the ID of the logical processor that the request is associated with. When a modified line is being pushed back to system memory to make room for a new line being read into the cache, the line write transaction uses the ID of the logical processor whose code caused the read of the new line. When a code read transaction is initiated on the FSB at the request of ...
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