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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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PAT Feature (Page Attribute Table)

What's the Problem?

As previously discussed in “MTRRs Added” on page 572, it is imperative that the processor core know the proper way to behave when performing a memory access within any given region of memory space. The BIOS can program the memory type for each memory range into the MTTRs at startup time.

When the OS sets up the Page Directory and the Page Tables associated with each task, it uses the PCD and PWT bits in each PDE and PTE to define the memory type for the page of memory space:

  • In the PTE that defines the mapping of a 4KB memory page, the PCD and PWT bits are used to define the page's memory type.

  • In a PDE that defines the mapping of a 4MB memory page, the PCD and PWT bits are used to define ...

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