July 2004
Intermediate to advanced
1744 pages
35h 3m
English
There is more transaction-related information to be output during the Request Phase than there are signals in the Request Phase signal group (see Figure 49-4 on page 1209). To address this problem, the same signal group is used to output the two packets that comprise the transaction request. Different information is output on these signals in each of the two packets.

In some Intel® documentation, the information output in the two packets is referred to in the following manner:
The information output on the address (A[35:3]#) ...
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