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The Unabridged Pentium 4 IA32 Processor Genealogy
book

The Unabridged Pentium 4 IA32 Processor Genealogy

by Tom Shanley, Bob Colwell
July 2004
Intermediate to advanced
1744 pages
35h 3m
English
Addison-Wesley Professional
Content preview from The Unabridged Pentium 4 IA32 Processor Genealogy

Chapter 17. Caching Overview

The Previous Chapter

This chapter provided a detailed description of the Debug register set. This description is directly applicable to all subsequent IA32 processors. This feature was enhanced starting with the advent of the Pentium® processor and a detailed description of the enhancement can be found in “Debug Extension” on page 497.

This Chapter

This chapter is for those who feel the need for a primer on cache memory. For those who don't feel the need for it, please move on to the next chapter. It occupies this place in the book because the next two chapters cover the 486 processor, the first IA32 processor to incorporate an integrated cache.

The Next Chapter

The next chapter provides a description the 486 processor's ...

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Publisher Resources

ISBN: 032124656XPurchase book