July 2004
Intermediate to advanced
1744 pages
35h 3m
English
To conserve on power consumption during a period of time when the processor is not needed, the chipset can assert the STPCLK# input to the physical processor. This has the following effects on an HT-capable processor:
When asserted, the core transitions to the Stop-Grant power conservation state (see “The Stop Grant State” on page 688). Program execution is halted but the core continues to service snoops.
All logical processors stop program execution and none of them respond to any interrupts.
In an MP system, this pin on all physical processors are usually tied together, so the assertion of STPCLK# affects all logical processors in the system simultaneously.
These two signals are inputs ...
Read now
Unlock full access