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The Unabridged Pentium 4 IA32 Processor Genealogy by Bob Colwell, Tom Shanley

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The Snoop Phase Duration Is Variable

Refer to Figure 50-3 on page 1232. The Snoop Phase begins immediately after the Request Phase completes (clocks 2, 4, and 6) and completes when a valid snoop result (something other than both HIT# and HITM# asserted) is presented to the Request and Response Agents by the Snoop Agents. Table 50-1 on page 1232 defines the meaning of the various snoop results. The following provides a clock-by-clock description of Figure 50-3 on page 1232 (an example of three back-to-back memory transactions):

  1. In BCLK cycle 1:

    - Transaction one is initiated.

    - All FSB agents latch packets A and B of transaction 1. Packet A provides all of the information necessary to perform a snoop (i.e., the memory address and the transaction ...

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