The Unabridged Pentium 4 IA32 Processor Genealogy

A Very Simple Example Scenario

Assume that the platform logic (i.e., the chipset or the system board logic) detects a condition that requires management by the SM handler program (see “What Falls Under the Heading of System Management?” on page 1465 for some examples). In response, an SMI is generated to the processor. The following sequence of events occurs (this description assumes that the processor is a Pentium® Pro or a subsequent IA32 processor):

1. The processor recognizes the SMI on the next instruction boundary and suspends execution of the currently executing program.

2. The processor generates a Special transaction on its FSB and outputs the SMI Acknowledge message on its Byte Enable outputs to inform the chipset that until the processor ...