The Unabridged Pentium 4 IA32 Processor Genealogy

Chapter 41. Pentium^® 4 Handling of Loads and Stores

The Previous Chapter

This chapter provided a detailed description of the Pentium® 4 caches. This included:

• Determining the Processor's Cache Sizes and Structures.

• Enabling/Disabling the Caches.

• The L1 Data Cache.

• The L2 ATC.

• The Hardware Data Prefetcher.

• The L3 Cache.

• FSB Transactions and the Caches.

• The Cache Management Instructions.

This Chapter

This chapter provides a detailed description of load and store operations and includes:

• The Memory Type Defines Load/Store Characteristics.

• The Load Buffers.

• Loads from Cacheable Memory.

• Loads Can Be Executed Out-of-Order.

• The L1 Data Cache Implements Squashing.

• Loads from Uncacheable Memory.

• The Definition of a Speculatively Executed Load.

• Replay.

• Loads and the ...