The Unabridged Pentium 4 IA32 Processor Genealogy

The Trace Cache

IA32 processors prior to the Pentium® 4 processor implemented an L1 Code Cache. IA32 instructions were fetched from memory, stored in the L1 Code Cache and then fed into the processor core's instruction pipeline for execution. Prior to the advent of the Pentium® Pro processor, the processor core executed the IA32 instructions themselves.

In the P6 processor family, the IA32 instructions were sourced to the instruction pipeline from the L1 Code Cache and, several stages into the pipeline, were decoded into fixed-length μops which were provided to the execution units.

Each time that the currently executing program requested code that was already in the code cache, the IA32 instructions had to be decoded into μops again before they ...