Engineering Digital Design

8.9 DUAL-RAIL SYSTEMS AND ALUs WITH COMPLETION SIGNALS 379

FIGURE 8.47

The J th 1-bit arithmetic module for a PALU with completion signal and CLA capability according to

Eqs. (8.29) and (8.30). (a) Logic circuit showing carry propagate, and dual-rail carry generate, carry

inputs and result signals. (b) Block circuit symbol for the logic circuit in (a). (c) Completion/result

logic circuit for combined logic and arithmetic modules.

The PALU can be completed by combining the logic module in Fig. 8.42 with the arith-

metic module of Fig. 8.47. This requires that the completion signals from the logic module,

T

1

and T

0

, be combined with the completion/result ...