Engineering Digital Design

PROBLEMS 611

FIGURE P12.6

(a) Construct the state diagram and state table for this counter.

(b) Design this counter by using the hardware indicated in Fig. P12.6b (nothing

else), and end with a logic diagram. Plan to initialize into the 0000 state and

take the count from the Q(H) outputs. (Hint: Review Fig. 12.39 and read the

discussion at the end of Section 12.5.)

(c) Alter the design slightly to provide cascading capability for this counter.

12.21 At the discretion of the instructor, simulate by using EXL-Sim2002 any problem

in this chapter where simulation is appropriate. Thus, an assignment 12.21/12.17b

requires that the resulting logic circuit of ...