Engineering Digital Design

380 CHAPTER 8 / ARITHMETIC DEVICES AND ARITHMETIC LOGIC UNITS (ALUs)

FIGURE 8.48

The three least significant bit stages of an n-bit arithmetic module for a PALU with CLA and comple-

tion signal capability showing the carry generate/propagate (CGP) network required for the dual-rail

carries and carry generate parameters.

logic 0 (G

0

, P



), as required for dual-rail carries. This is demonstrated in Fig. 8.48, where

for simplicity only the arithmetic module is featured. Notice that the carry-in’s for the

LSB stage are properly initialized for addition or 2’s complement arithmetic. Hence, for

subtraction,

Add/Sub = 1 introduces a logic 1 into C

in

1 and a logic ...